1. Field of the Invention
The present invention relates to a digital PLL circuit, and more particularly relates to a method of initial setting of a digital PLL circuit employed in digital communication using for example GMSK (Gausian filtered Minimum Shift Keying).
2. Description of the Related Art
In multi-directional communication systems in which communication is performed in bursts, systems using PSK (Phase Shift Keying) modulation are common. In such PSK systems, drift of the frequency of the carrier wave (i.e. frequency offset) produces phase demodulation distortion, which severely impacts the symbol error rate characteristic. A device is therefore necessary to automatically compensate for the amount of phase rotation produced by frequency offset.
A receiver having means for removing the effect of frequency offset, such as phase synchronization detection devices etc. have been proposed including phase-locked loop (PLL) type devices. In these devices, the frequency of oscillation of a phase-locked oscillator is made to automatically track the input frequency by regenerating the carrier wave and performing phase comparison between the regenerated wave and the input wave. The relationship of input signal to noise ratio, and error rate in such a synchronized detection device is said to be superior to that of differential detection.
A type of PLL type phase-locked detection devices that has recently attracted attention is the digital PLL (DPLL). This is due to the characteristic features of a digital PLL, namely that, compared with an analog PLL, it has a larger capture range, is less effected by oscillations of the input signal, and can easily be implemented as an integrated circuit IC.
FIG. 1 shows an example of a prior art DPLL circuit. This DPLL circuit is called a phase calculation signal processing type DPLL, and is constituted of an angle calculation circuit 111 that finds the phase angle .theta. of the signal from the in-phase component (I) and quadrature component (Q) from a sub-synchronous detection unit (not shown), a subtractor 112 adapted to function as a phase comparison circuit, a phase adjustment circuit (MOD) 113, a loop filter 114, and a numerically controlled oscillator (NCO) 115. Further characteristic advantages of this DPLL, circuit are that it has excellent noise characteristics and synchronization characteristics, and enables high carrier frequencies to be used. Such a DPLL circuit is described in "Examples of design of PLL control circuits" edited by M. Hata, published on 18 Dec. 1987.
Although such a digital PLL is superior to an analog PLL in many respects, it does have the drawback that it requires a lock-in time usually corresponding to a few tens of symbols. Various proposals have been made to reduce this lock-in time of a digital PLL.
For example, Japanese Unexamined Patent Publication No. SHO 64-48519 entiled "DPLL circuit whose lock-in time can be automatically controlled" discloses a circuit, as shown in FIG. 2. It may be noted that the DPLL circuit of FIG. 2 differs from the DPLL circuit of FIG. 1 in that it represents a direct conversion of the analog PLL circuit form into a signal processing form.
In the DPLL circuit of FIG. 2, apart from the phase comparator 121 that compares the phases of the input timing signal and the reference clock, there is provided a phase difference detector 122 that detects the phase difference of these two signals. Reduction in the lock-in time is achieved by adjusting the rate by adding pulses to the pulse train from fixed oscillator 123 or removing pulses from this pulse train, in accordance with the phase difference detected by phase difference detector 122.
In more detail, the DPLL circuit shown in FIG. 2 comprises a phase comparator 121, phase difference detector 122, fixed oscillator 123, sequential loop filter 124, pulse addition or removal accelerator 125, pulse addition or removal circuit 126, and frequency divider 127.
Phase comparator 121 compares the phase of the timing signal that is received as input and the reference clock obtained by feedback. Binary quantization to -1 or +1 of the phase lead/lag with respect to the timing signal of the reference clock is then performed in each cycle of the carrier wave.
In accordance with the output of phase comparator 121, sequential loop filter 124 outputs a +1 pulse in a prescribed period whilst the reference clock lags the input timing signal and outputs a -1 pulse in a prescribed period whilst the reference clock leads the input timing signal.
Phase difference detector 122 detects the phase difference between the input timing signal and the reference clock. It then outputs a gate control signal corresponding to the detected phase difference to pulse addition or removal accelerator 125.
Pulse addition or removal accelerator 125 turns a gate on or off in response to a gate control signal from phase difference detector 122 to control the number of pulses from sequential loop filter 124. That is, pulse addition or removal accelerator 125 outputs all or some of the input pulses to pulse addition or removal circuit 126 depending on the gate control signal.
Pulse addition or removal circuit 126 receives pulses that are input from pulse addition or removal accelerator 125 and, in the case of +1 pulses, adds pulses of a number corresponding to the number of these pulses to the pulse train that is input from fixed oscillator 123. And in the case of -1 pulses, it removes pulses of a number corresponding to the number of these pulses from the pulse train that is input from fixed oscillator 123. The new pulse train that is thus obtained is then subjected to frequency division by frequency divider 127 and output as the reference clock.
Thus, in the DPLL circuit of FIG. 2, shortening of the lock-in time can be achieved if, when the phase difference between the timing signal and the reference clock is large, the number of pulses added or removed is made larger (i.e. if the frequency of operation is raised). Also, by raising the frequency of operation, jitter can be reduced.
A first problem with the conventional DPLL circuit is that attempts to shorten the lock-in time result in excessive increase in the size of the circuit.
The reason for this is that two phase comparators are necessary and, furthermore, a circuit such as a pulse addition or removal accelerator is required.
A second problem of the conventional DPLL circuit is that overshoot of the output phase of the phase comparator cannot be suppressed, so considerable time is required for lock-in.
The reason for this is that setting of the initial values etc. is not performed in the initial lock-in period.